So-called “domino” logic circuits are often used in semiconductors because of their superior speed and area characteristics as compared to static circuits.
FIG. 1 shows a generic example of a domino logic circuit 10. Input signals comprise a clock signal CLK and one or more inputs I. It will be understood that the clock signal CLK may be a square wave or a regularly oscillating signal. An output O is driven by an inverter 11. The input of inverter 11 is driven by an intermediate node 12. A pullup transistor 13 raises node 12 to Vdd when CLK is low.
Operation of circuit 10 occurs in two phases: a precharge phase and an evaluation phase. The precharge phase occurs when CLK is low. During this phase, pullup transistor 13 is on, and node 12 is charged to high. Output O, comprising the output of inverter 11, is therefore low. A keeper transistor 14 is gated by O, and pulls node 12 high whenever output O is low.
The evaluation phase occurs when CLK goes high and pullup transistor 13 is turned off. In this phase, a lower transistor 15 is turned on, enabling a pull-down network 16. The pull-down network 16 is responsive to inputs I to potentially pull down node 12, depending on the state of inputs I. In the situation where pull-down network 16 does not pull node 12 low, keeper transistor 14 maintains node 12 at a high level, and output O is therefore maintained at a low level.
Domino logic circuits such as this, also referred to as “sequentials,” are often chained in real-world circuits. That is, the output of one such circuit is connected to the input of another. When developing and debugging circuits such as these, it is desirable to be able to read each output and also to set each output to an arbitrary state. This is often accomplished by the use of so-called “scan” circuitry.
FIG. 2 shows a simplified example of how such scan circuits work in conjunction with domino logic circuits. This example includes a plurality of domino logic circuits 18, with outputs chained to inputs of succeeding logic circuits. A scan circuit 19 is associated with each logic circuit 18. Each scan circuit 19 has a scan data connection 20 to the output of the associated logic circuit 18. If desired to read the outputs of the logic circuits, the scan circuits 19 are configured to act in unison to read and store all output values. Subsequently, the stored output values are shifted serially through each scan circuit 19 to a single output pin.
If desired to write or set the outputs, the desired values are first shifted serially into the scan circuits 19. Then, a scan line 21 is asserted from each scan circuit 19 to each corresponding logic circuit 18. This causes the logic circuit 18 to tri-state its output. The scan data connections 20 are then set at the desired levels. Operation of the overall circuit can then be initiated from this known start point.
FIG. 3 shows how the domino logic circuit of FIG. 1 is modified for use with the scan circuits of FIG. 2. The circuit of FIG. 3 is the same as that of FIG. 1, except that a scan line SC is added as an input to inverter 11. Inverter 11 is configured to tri-state its output in response to scan line SC.
It is often the case that domino logic interfaces with static logic circuits or elements. In a static logic circuit, the output is expected to change only at a given clock transition, and to then remain valid and stable until a subsequent clock transition.
FIG. 4 shows a prior art circuit 30 that interfaces between domino logic and static logic. Circuit 30 receives domino logic signals as its input, and produces a signal that is compatible with static logic. This type of circuit is referred to as a “domino-exit” circuit.
The circuit 30 includes two portions: a dynamic signal receiver portion 31 and an output driver portion 32. The dynamic signal receiver portion 31 includes a PMOS transistor 106, an NMOS transistor 108 and an NMOS transistor 110 coupled in series between Vcc and Vss. The gates of the PMOS transistor 106 and the NMOS transistor 108 are coupled to a line IN_H, while the gate of the NMOS transistor 110 is coupled to line CLK. In addition, the drain of NMOS transistor 110 and the source of NMOS transistor 108 are coupled to a line 112.
The output driver portion 32 of circuit 30 includes a PMOS keeper transistor 114 with its source connected to Vcc and its drain connected to memory node 115. Line OUT_L as well as an input to a tri-stateable inverter 116 are also coupled to OUT_L. The inverter 116 can be tri-stated by a low signal applied to line SCA. It will also be understood that the inverter 116 could be tri-stated by a high signal or by complementary signals.
The output of inverter 116 is applied to (1) the gate of PMOS keeper transistor 114, (2) the gate of an NMOS transistor 118, and (3) scan line IN_OUT. The source of NMOS transistor 118 is coupled to Vss, while the drain is coupled to line 112.
Circuit 30 can operate in a precharge phase and an evaluation phase. During the precharge phase, line CLK is held low while line IN_H is high. As a result PMOS transistor 106 and NMOS transistor 110 are turned off, thus precluding signal receiver portion 31 from having any influence over the output driver portion 32.
During the precharge phase, it is possible for scan circuitry to read or change the value stored on the memory node 115. For example, in order to read the value latched on the output driver portion 32, the diagnostic testing circuit 102 need only read the value applied to the line IN_OUT. This value will be the complement of that stored on the memory node 115.
In order to write a new value to be latched on the memory node 115, a low signal may be applied to line SCA, resulting in the inverter 116 being tri-stated. Once this occurs, the value sought to be latched to the memory node 115 may be applied to the line IN_OUT. Line SCA may then be raised, and the driver portion 32 will maintain this new value.
During the evaluation phase, line CLK delivers a high signal, while line IN_H may be either high or low to indicate a data value. In this situation, transistors 106 and 108 act as an inverter to drive node 115 (and output OUT_L) to a value that is complementary to that of input line IN_H, and to potentially change the value at node 115.
Operation of this circuit relies on the relative sizes or impedances of the receiver circuits and the driver circuits. Specifically, the receiver circuits are relatively bigger than the driver circuits so that the receiver can effectively overwrite the feedback loop present without driver portion 32. FIG. 5 shows a prior art representation of a circuit 200 that interfaces between static logic and domino logic. Circuit 200 receives a static logic signal at its input and produces signals compatible with domino logic. This type of circuit is referred to as a “domino-entry” circuit. The circuit 200 includes two sub circuits—a capture latch 201 and a domino converter 202. Capture latch 201 includes a PMOS pullup transistor 203, and NMOS pulldown transistors 204, 206, 208 connected in series between Vcc and Vss. A line CLK is coupled to the gates of PMOS transistor 203 and NMOS transistor 204. Line CLK is also connected to NMOS transistor 208 through an inverter 210. A line IN_H is coupled to the gate of NMOS transistor 206.
Domino converter 202 includes a latch formed by a cross-coupled inverter pair 212, 214. A latch node 216 couples the domino converter 202 to the capture latch 201.
Circuit 200 can operate in a precharge phase and an evaluation phase. During a precharge phase, line CLK is low. This turns on pullup transistor 203 and turns off pull down transistor 204. As a result, a high signal is coupled to the inverter pair 212, 214 and a low signal is applied to line OUT.
During an evaluation phase, line CLK is asserted high, turning off pullup transistor 203 and turning on pull down transistor 204. Also, since a propagation delay is encountered at the inverter 210 before a low signal is coupled to PMOS 208, there exists a finite period in which both gates 204 and 208 are turned on. Thus, if line IN_H is asserted high, then NMOS transistor 206 is turned on, and a low signal pulse from Vss is coupled through NMOS transistors 208, 206, 204 to latch node 216. The signal pulse is then inverted to a high signal by inverter 212 before being applied to line OUT.
Alternately, if a low signal is applied to line IN_H, NMOS transistor 206 is turned off. Thus Vcc and Vss in capture latch 201 are decoupled from the input node 216 and the value latched in the cross-coupled inverter pair 212, 214 is output on line OUT.